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W33D0160 160-DOTS LCD DRIVER WITH CLOCK FUNCTIONS
GENERAL DESCRIPTION
This chip is a LCD driver for a telephone dialer number display or other equipment. A maximum of 20 digits or 160 dots can be displayed, with 1/3 bias, 1/4 duty, and 40 segments. In normal mode, there are max. 160 dots (can be programmed by P) can be displayed on the LCD panel. In clock mode, the LCD panel can display a built-in clock that can be read out by P. A VDD1 pin is used in different voltage system application to implement voltage level shift function so the transceiver data can be guaranteed. This chip is fabricated using Winbond's high performance CMOS technology.
FEATURES
* Supply voltage: 1.2V-1.7V or 2.4V-3.4V by mask option. * Operating frequency: 32.768 KHz. * Built-in crystal oscillator circuit. * Voltage level shift with a P. * Two operating modes:
- Normal mode (can be written by P). - Clock mode (can be read out by P).
* Max. 20 (160 dots) digits with 8 dots/digit displayed in normal mode. * LCD (160 dots) can be programmed by P from address 0. * Clock display include leap-year, month, date, hour, minute, and sec. * Clock adjustable through MODE, SET pins. * Clock 12 or 24 format by pin select. * 1/3 bias, 1/4 duty 40-segment LCD panel. * Built-in VDD1 for different voltage system data transceiver application. * Casecade function performed with Master/Slaver function option by mask option.
TYPE NO. W33D0161 W33D0163 W33D0165 W33D0166
OPERATING VOLTAGE 1.5V-1.7V 2.4V-3.4V 1.2V-1.7V 2.4V-3.4V
OSCILLATOR 32.768 KHz Crystal 32.768 KHz Crystal Slaver Slaver
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Publication Release Date: May 1999 Revision A4
W33D0160
PIN CONFIGURATION
33
64 1
20
PIN DESCRIPTION
SYMBOL OSCI OSCO VDD VDD1 VSS VLCD1 VLCD2 CP, CN TEST1 RST COM1COM4 PIN 38 37 35 45 39 49, 48 50, 51 36 34 52-55 I/O I O I I I I I I I O FUNCTION Oscillator input pin. Connect to 32.768 KHz crystal. External capacitor is needed. Oscillator output pin with internal capacitor. Positive power supply. For voltage level shift during data transceiver. Negative power supply. LCD voltage pins. Connect a capacitor to both pins, used for the LCD double voltage capacitor. Test pin with pull-low resistor. Not use. Chip reset input pin. Active low with internal pull-high resistor. LCD panel common pins. (1/3 bias, 1/4 duty)
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W33D0160
Pin Description, continued
SYMBOL SEG1SEG40 RDATA RCLK WDATA WCLK MS
PIN 56-64, 1-31 43 41 44 40 42
I/O O O I I I I LCD panel segment pins. (1/3 bias, 1/4 duty)
FUNCTION
CMOS type serial data output pin. Power source: VDD1 Synchronous read clock input pin. Power source: VDD1 Serial data input pin. Power source: VDD1 Synchronous write clock input pin. Power source: VDD1 Mode select input pin with floating status. Normal mode is active high or low by mask option. In this SPEC description MS pin high active for the normal mode display. Power source: VDD1 (Refer to functional description for more detail) 12-hour (high) or 24-hour (low) clock select pin with floating status. Power source: VDD1 Waveform generator output pin. When RST = 0, 1 Hz square-wave will output from this pin. When RST = 1, 1 Hz square-wave will output from this pin. Power source: VDD1 Clock mode-adjust pin with internal pull-low resistor. Clock digit-adjust pin with internal pull-low resistor.
12 / 24 WFG
46 47
I O
MODE SET
32 33
I I
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Publication Release Date: May 1999 Revision A4
W33D0160
BLOCK DIAGRAM
WFG COM1 COM2 COM3 COM4 COMMOM CIRCUIT OSCO OSCI TEST1 MODE SET TIME BASE SEGMENT LATCH & DECODER & MUX SELECT 1/3 Bias 1/4 Duty
STATE CONTROL
WATCH CLOCK
SEG1 | SEG40
MS 12/24 VDD1 VDD VSS RDATA RCLK WDATA WCLK RST
CONTROL CIRCUIT SHIFT REG LATCH REG.
SCAN CKT
VOLTAGE DOUBLER
VLCD1 VLCD2 CUP1 CUP2
FUNCTIONAL DESCRIPTION
1. Operating Mode
The W33D0160 series LCD driver provides two operating modes: Normal mode, and Clock mode. The Normal mode data can be written by P only, but the Clock mode data can be read out by P and can be adjusted by the manual method through the MODE and SET pins. According Figure 1 the address 0-159 range works as the LCD data range and the address 160-167 work as the LCD control range. User must program the data over 168 clks to update all the data in the memory at one time, and the last 168 data will be the final data that can remain in the LCD data memory. In this case the last-in data that over 168 data will be the data of the address 167. All the data in the location 0-167 can only be written by the WCLK and WDATA pins, and can not be read out. In this chip only the Real-Time-Clock data can be read out by the RCLK and RDATA pins.
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W33D0160
The following table are the LCD data memory address mapping that can be written through the WCLK and WDATA pins, and the Real-Time-Clock data memory address mapping that can be read out through the RCLK and RDATA pins.
1.1.1 The write function address mapping definition (Normal mode)
(LCD data memory addressing mapping) ADDRESS 0-159 FUNCTION 160 dots LCD panel display location, the first clk will define the address 0 data in the memory, but when the clk over 168 clks the first address will shift out, and keep the last 168 data in the memory. Normal mode LCD panel ON/OFF control bit. (This bit will not affect the normal data in the chip, it just light on/off the LCD panel in the Normal data but not the Real-Time-clock data) 0: LCD panel light on.(Default value) 1: LCD panel light off. 161 Clock bit (This bit can disable or enable the Clock mode) 0: Clock mode can be shown on the LCD panel. (Default value) 1: Clock mode can not shown on the LCD panel. 162-167 Reserved.
160
1.1.2 The read function address mapping definition ( Clock mode) (The Real-time-clock data memory addressing mapping) ADDRESS 0-7 8-15 16-23 24-31 32-39 40-47 Month data memory range Day data memory range Hour data memory range Minute data memory range Second data memory range Leap year data memory range FUNCTION
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Publication Release Date: May 1999 Revision A4
W33D0160
1.2 The transceiver function controlled by a P:
The W33D0160 series LCD can display the data on LCD panel which is input by a serial transmission function from an external device such as a microprocessor. In Normal mode, the data can be written by a P with transmission function at the rising edge of WCLK pin. In the Clock mode the Real-TimeClock data can be read out by a P with the receive function at the rising edge of RCLK pin. The RCLK pin and WCLK pin must be set to high state normally if there is no data reception and transmission. 1.2.1 Switch between Read and Write Function When in write function, the first falling edge of RCLK will switch the write function to read function then P can read data from the RCLK pin and RDATA pin, and vice versa. Refer to Figure 2. When the write function is re-active (changed from read function to write function or the power on reset), the WCLK clock input to the chip will reset the write-starting address to 0. In the same case the read function is re-active (changeed from write function to read function or the power on reset) The RCLK clock input to the chip will also reset the read-starting address to 0. Please refer to Figure 3 and Figure 4. 1.2.2 Serial Data Written by P A P can send serial data and clock to through the WDATA pin and WCLK pin, respectively to control the LCD panel. When P want to write data to the chip in Normal mode, firstly, P must do a dummy read function or change read mode from write mode or pull MS pin from low to high to reset the writestarting addresss to 0, after this procedure the serial clock will sent by P to set the LCD memory for the LCD display. In this time, P sends the serial data to the chip by the WDATA pin and WCLK pin, and W33D0160S will store the serial data from the starting address and the address is increased by one when the WCLK pin receives one clock form P. Refer to Figure 3. The LCD memory describe as above can not be read out from W33D0160. 1.2.3 Serial Data Read by P P can only read out the Real-Time-Clock data from the RCLK and RDATA pins. Each time when the write mode change to read mode or pull the MS pin to low from high or do a dummy write function the Real-Time-Clock address will be reset to address 0, then input the clock to the RCLK pin, the RealTime-Clock data will be sent out from RDATA pin. The Real-Time-Clock data will output with the format as Month, Day, Hour, Minutes, Second and Leap-year. So there are only total 48 clocks can output all of the RTC memory data. The clock over the 48 will output the first memory in the RTC memory that will be the Month data. The function of the two operating modes are described as below:
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W33D0160
1.3 Normal mode:
MS pin pull high will make the LCD to show the normal data in the LCD panel, but no matter MS is high or low the rising edge on WCLK will write the the normal data to the LCD memory and the rising edge on RCLK will read out the Real-Time-Clock data memory. The rising edge of the MS pin will also reset the address in the LCD memory to address 0, so in this case we can ommit the dummy read in the write procedure. Because the LCD memory locate on the range of 0 to 159 and the LCD control memory locate on the range of 160 to 167, the first digit is shown in the most left place on the LCD panel. When P write data to W33D0160S in normal mode, firstly, P must reset the starting address to 0 , then P can write one bit to W33D0160S while the WCLK pin receives one clock from P and the address is increased by one after each one write clock input, as the address increase to 167, the next address is reset to 0, then the address increase continuously if WCLK pin keeps on receiving clock from P. When P write data to W33D0160S more than 168 clocks with 160 dots at a time, the 169th clock will input the data to the first dot, and the rest can be done in the same manner. Refer to Figure 1. Which operating mode is selected by MS pin, and Clock bit, where the Clock bit can be programmed by P, the Clock bit locates on the address of 161.The default value of all the LCD control bits are "0". Table 1 indicates the relation between operating mode and MS pin, and Clock bit.
1.4 Clock mode:
When the MS pin is pulled to low (by mask option), the Real-Time-Clock data will be shown on the LCD panel. As Table 2 the clock mode can display the leap-year, month, date, hour, minute and second. The RTC data will be shown on the LCD panel of the digit 3, 4, 6, 7, 11, 12, 14, 15, 17, 18, and 20. The other digits will keep the data as the Normal status before switch to Clock mode. That means if you want to show the only RTC data you must clear firstly all the Normal memorys or digit 1, 2, 5, 8, 9, 10, 13, 16, and 19 also you can control the Normal mode LCD ON/OFF control bit to 1 on the address of 160. Please refer to Figure 8. The Real-Time-Clock data can only be adjusted by the Manual adjusting method through the MODE and SET pins. The following is the Manual adjusting method description. 1.4.1 Manual adjusting method through the MODE and SET pins. When the Clock mode is entered (MS = low) , the current time is displayed on the LCD panel. Keep the MODE pin depressed (High Active) will cause the month digits to begin flashing. The SET pin can be used to adjust the month setting; the setting will increase by one with each trigger from the SET pin. When the MODE pin is released, the month digits will continue flash. At this time, a new input on the MODE pin will cause the date digits to begin flashing, and the date can then be set. Successive inputs on the MODE pin will cause the hour, minute, and leap-year but no second digits to flash, allowing the hour, minute, and leap-year but no second data to be adjusted. While the leap-year digits are flashing, an input on the MODE pin will return to clock mode. While the clock setting is being adjusted at any time if there is no signal on the MODE pin for more than 15 seconds, it will return to clock mode automatically.
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Publication Release Date: May 1999 Revision A4
W33D0160
If the SET pin is depressed and held down over 2 seconds, the clock setting will speed up at an interval of 125 mS. When the SET pin is ever depressed during the clock adjusting mode, the clock will be restarted from the new setting time with the second data reset to 0. The clock mode will automatically return to nonflash status from flash status if the flash status flash over 15 sec and no any key be depressed. The MODE and SET pins are both high active. Refer to Figure 7.
2. Reset function
There are two methods to initialize the chip: one is power-on reset, the other is pulling the RST pin to low (low active).
2.1. Power-On Reset
At power on reset , the power-on reset circuit will generate a pulse to reset the chip. All LCD segments will flash momentarily about 2 seconds and the built-in clock will start from < 1 1 > and < 00 00 00 > and the 160 dots will be reset to "0".
2.2. RST Pin function
Pulling RST to low will reset all of the chip's functions except the clock memory, and all LCD segments will flash momentarily about 2 seconds and the 160 dots will be reset to "0".
3. LCD FORMAT
The LCD panel is 1/3 bias, 1/4 duty. Refer to Figure 9 and Figure 10. The LCD format is shown in Figure 11.
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage to Ground Potential Applied Input/Output Voltage Power Dissipation Ambient Operating Temperature Storage temperature RATING -0.3 to +7.0 -0.3 to +7.0 120 -20 to +70 -55 to +155 UNIT V V mW C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
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W33D0160
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
VDD-VSS = 1.5V, FOSE = 32.768 KHz, TA = 25 C
PARAMETER Op. Voltage1 Op. Voltage2 Op. Current1 Op. Current2 SEG1-SEG40 Source Current SEG1-SEG40 Sink Current COM1-COM4 Source Current COM1-COM4 Sink Current WFG Source Current WFG Sink Current Pull-high Resistor Pull-low Resistor Input Low Voltage Input High Voltage RDATA Drive Current
SYMBOL VDD1 VDD2 IDD1 IDD2 ISH ISL ICH1 ICL1 ICH2 ICL2 RH RL VIL VIH IRDD
TEST CONDITIONS No load, VDD = 1.5V (Crystal mode) No load, VDD = 3.0V (Crystal mode) VOH = 1.2V VOL = 0.3V VOH = 1.2V VOL = 0.3V VOH = 1.2V VOL = 0.3V RST MODE, SET VDD = 3.0V
MIN. 1.2 2.4 -0.4 0.4 -4 4 0 0.7 VDD -
TYP. 1.5 3.0 5 5 500 500 1000 1000 0.4
MAX. 1.7 3.4 10 10 2000 2000 0.3 VDD VDD -
UNIT V V A A mA mA mA mA A A Kohm Kohm V V mA
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Publication Release Date: May 1999 Revision A4
W33D0160
AC CHARACTERISTICS
PARAMETER Op. Frequency LCD Frequency SYMBOL FOSC FLCD VDD 1.5 TEST CONDITIONS Crystal Mask Option MIN. Rising Debounce Time Falling Debounce Time MODE to SET Effect Time Slow Adjust Effect Period Quick Set Data Time Quick Set-up Time RST Active Low Width Serial Transmit Data Setup Time Serial Transmit Data Hold Time Serial Receive Data Access Time RCLK Period, WCLK Period Transmit/Receive Time Oscillator Start Up Time WFG Duty Cycle TRD TFD TMS TSPD TQD TQS TRWD TDS TDH TAS TCLK TTRN TSTD TDCYL MODE, SET (Crystal Mode) MODE, SET (Crystal Mode) 35 35 1 1 2 50 50 50 150 2 TYP. 32.768 16 32 64 125 1 3 50 MAX. 1999 UNIT KHz Hz Hz Hz mS mS mS mS mS S S nS nS nS nS mS S %
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W33D0160
Table 1 The function table of three modes
MS pin 0 0 1 1
ps: 1. '' represent 'function existed'. 2. '' represent 'function not existed'. 3. MS pin high or low active can be select by mask option.
CLOCK bit 0 1 0 1
CLOCK MODE Read out Display-ed
NORMAL MODE Write Display-ed
Table 2 The Address Mapping of Clock Mode Mon. Date
10
Address corresponding to digit
0-7 0 4 | | 3 7
10
8-15 12 8 | | 15 11
Hour
Min.
Sec.
Leap Year
10
Address corresponding to digit
16-23 20 16 | |
10
24-31 28 24 | |
10
32-39 36 32 | |
P
40-47 44 40 | |
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Publication Release Date: May 1999 Revision A4
W33D0160
The address corresponding to the first displayed digit of Sec/Min./Hour/Date/Mon. Address 4-7/ 12-15/ 20-23/ 28-31/ 36-39 0000 0001 0010 0011 0100 0101 Others None(M/D), (H/Mi/S) 1 (M/D/H/Mi/S) 2 (D/Mi/H/S) 3 (D/Mi/S) 4 (Mi./S) 5 (Mi./S) #(M/D/H/Mi/S) H dot of 20th digit * None None None # Displayed Digit The address corresponding to the 2nd displayed digit of Sec/Min./Hour/Date/Mon. Address 0-3/ 8-11/ 16-19/ 24-27/ 32-35 0000 0001 0010 0011 0100 0101 0110 0111 40-47 0000 0001 0010 0011 Others
Ps: 1. (M/D/H/Mi/S) means "for Mon. or Date or Hour or Min. or Sec.". 2. "" : Displays "0" or none by mask option 3. "#" : Represent an illegal programming data 4. "*" : Represent a leap year
Displayed Digit
0 1 2 3 4 5 6 7 8 9 #
1000 1001 Others
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W33D0160
0 160 DOTS for LCD data
159 160 Control bits
167
Figure 1. Address Format
WRITE FUNCTION WDATA
READ FUNCTION
WRITE FUNCTION
WCLK
change function
RDATA RCLK change function
Figure 2. Read/Write Change Function
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Publication Release Date: May 1999 Revision A4
W33D0160
dummy read write the serial data from the address 0 2nd digit AE AE
MSB
WDATA
LSB
1st digit
20th digit
Serial Data WCLK RDATA
TTRN
RCLK
TDS
Data Valid
TDH
WDATA
A WCLK
B
C
D
E
F
G
H
TCLK
A F E G D B C H seg n+1 seg n
Figure 3. Write Function Controlled By P
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W33D0160
Write function read the serial data (only the RTC data) from the starting address 0
WDATA
WCLK RDATA
RCLK
Total 48 clocks read out the RTC data
TAS RDATA TDH
A
RCLK
B
G
H
TCLK
Figure 4. Read Function Controlled By P
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Publication Release Date: May 1999 Revision A4
W33D0160
Clock Mode Normal Mode
Mode switch controlled by MS pin If Clock bit = 0 (MS = 1 : OFF Hook) (MS = 0 : ON Hook)
Mode enter
More than 15 sec
12 31 23 59 59
Mode enter
5
1 2 (Flash)
Mode enter
OFF-HOOK
57
(Flash) 3 1
Mode enter
2 3 (Flash)
Mode enter
ON-HOOK
577006
5 9 (Flash)
Mode enter
5770066712 4713171400
(Flash)
Max.20 digits can be dispalyed
Figure 5. Mode Chart
Mode Check
NO MS = 0 ?
YES
YES
NORMAL MODE
Clock bit = 0 ? NO
(display receive data)
Display data of normal mode only
CLOCK MODE
(display real time clock)
Figure 6. Flow Chart
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W33D0160
TRD
TSPD
TFD
MODE SET
NORMAL MODE
TMS
MON. flash
MON. MON. adj. flash
MON. MON. adj. flash
DATE flash
HOUR HOUR HOUR HOUR HOUR flash adj. flash adj. flash
MIN. flash
NORMAL MODE
SLOW ADJUSTING
TQS
TQS
MODE SET
NORMAL MODE MON. flash MON. flash DATE flash HOUR flash HOUR flash MIN. flash NORMAL MODE
QUICK ADJUSTING
Figure 7. Clock Adjusting
The digit 1, 2, 5, 8, 9, 10, 13, 16, and 19 will not be affected and will be the same as the final status in Normal mode.
Figure 8. LCD Clock Format
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Publication Release Date: May 1999 Revision A4
W33D0160
FLCD
(1/4 DUTY,1/3 BIAS)
COM1
V3 V2 V1 VSS V3 COM2 V2 V1 VSS V3 COM3 V2 V1 VSS V3 V2 COM4 V1 VSS V3 V2 V1 VSS V3 V2 V1 VSS VLCD COM1 - SEG1 (Selected Waveform) 1/3 VLCD VSS -1/3 V LCD -VLC COM1 - SEG2 (Non Selected Waveform) 1 Flame 1/3 VLCD VSS -1/3 VLCD
V1 = 1/3 VLCD V2 = 2/3 VLCD V3 = VLCD
SEG1
SEG2
Figure 10. LCD Waveform
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Publication Release Date: May 1999 Revision A4
W33D0160
SEG
digit 1
39 A B C H F G E D
digit 2
38 F G E D 37 A B C H
digit 3
36 F G E D 35 A B C H
digit 4
34 F G E D 33 A B C H
digit 5
32 F G E D 31 A B C H
digit 6
30 F G E D 29 A B C H
digit 7
28 F G E D 27 A B C H
digit 8
26 F G E D 25 A B C H
digit 9
24 F G E D 23 A B C H
digit 10
22 F G E D 21 A B C H
COM 40 1 2 3 4
SEG
digit 11 19 A B C H
digit 12 18 F G E D 17 A B C H
digit 13 16 F G E D 15 A B C H
digit 14 14 F G E D 13 A B C H
digit 15 12 F G E D 11 A B C H
digit 16 10 F G E D 9 A B C H
digit 17 8 F G E D 7 A B C H
digit 18 6 F G E D 5 A B C H
digit 19 4 F G E D 3 A B C H
digit 20 2 F G E D 1 A B C H
COM 20 1 2 3 4 F G E D
Figure 11. LCD Panel Format
The diagram of W33D0160S controlled by P is shown in Figure 13.
VDD
VDD1
VDD
Mode select Clock out
MS RCLK RDATA WCLK WDATA
P
Data in Clock out Data out
W33D0160S LCD driver
Figure 12. Application Suggestion
Noet: The condition that normal mode is enabled by setting MS pin high or low is mask option. Throughout all this spec., the normal mode is enabled when MS pin is high. VDD: W33D0160S Main power VDD1: Voltage source come from uP for level shift
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W33D0160
WCLK WDATA RCLK RDATA
W33D0160/0163
OSCI
OSCO
32768Hz
MS1 P MS1 MS2 MS3 OSCI WCLK WDATA RCLK
W33D0165/0166
OSCO
MS2 WCLK VDD1 WDATA RCLK
W33D0165/0166
OSCI
OSCO
MS3 To another piece
Figure 13. Normal Mode Cascade Application Circuit
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Publication Release Date: May 1999 Revision A4
W33D0160
BONDING PAD DIAGRAM
2 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 3 49 4 5 6 7 8 9 10 11 12 13 14 Y (0,0) X 48 47 46 45 44 43 42 41 40 39 38 37
Logotype
15 36 16 17 35 34 1819 20 21 22 23 24 25 26 27 28 29 30 31 32 33
Notes: 1. The substrate must be connect to VSS. 2. The chip size is 2550.00 x 2720.00 m2.
PAD LIST
PAD NO. PAD NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 SEG 18 SEG 19 SEG 20 SEG 21 SEG 22 SEG 23 PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 X -963.00 -1150.00 -1150.00 -1150.00 -1150.00 -1150.00 -1150.00 -1150.00 -1150.00 -1150.00 -1150.00 -1150.00 -1150.00 -1150.00 Y 1235.00 1091.40 955.20 819.20 683.00 547.00 410.80 274.80 138.60 2.60 -133.60 -269.60 -405.80 -541.80 PAD NO. PAD NAME 33 34 35 36 37 38 39 40 41 42 43 44 45 46 SET RST VDD TEST OSCO OSCI VSS WCLK RCLK MS RDATA WDATA VDD1 12 / 24 PIN# 33 34 35 36 37 38 39 40 41 42 43 44 45 46 X 945.30 1129.50 1129.50 1129.50 1129.50 1129.50 1129.50 1129.50 1129.50 1129.50 1129.50 1129.50 1129.50 1129.50 Y -1229.90 -1089.10 -947.30 -816.90 -677.90 -541.90 -402.90 -272.50 -130.70 -0.30 141.50 271.90 413.70 544.10
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W33D0160
Pad List, continued
PAD NO. PAD NAME 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SEG 24 SEG 25 SEG 26 SEG 27 SEG 28 SEG 29 SEG 30 SEG 31 SEG 32 SEG 33 SEG 34 SEG 35 SEG 36 SEG 37 SEG 38 SEG 39 SEG 40 MODE
PIN# 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
X -1150 -1150 -1150 -1150 -963.00 -826.80 -690.80 -554.60 -418.60 -282.40 -146.40 -10.20 125.80 262.00 398.00 534.20 670.20 809.20
Y -678.00 -814.00 -950.20 -1086.20 -1229.90 -1229.90 -1229.90 -1229.90 -1229.90 -1229.90 -1229.90 -1229.90 -1229.90 -1229.90 -1229.90 -1229.90 -1229.90 -1229.90
PAD NO. PAD NAME 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 WFG VLCD2 VLCD1 CP CN COM1 COM2 COM3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9
PIN# 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
X 1129.50 1129.50 1129.50 1129.50 942.50 809.20 667.40 537.00 395.20 262.00 125.80 -10.20 -146.40 -282.40 -418.60 -554.60 -690.80 -826.80
Y 685.90 819.10 955.30 1091.30 1235.00 1235.00 1235.00 1235.00 1235.00 1235.00 1235.00 1235.00 1235.00 1235.00 1235.00 1235.00 1235.00 1235.00
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Publication Release Date: May 1999 Revision A4
W33D0160
PACKAGE DIAMENSION
64-pin QFP
H D
64
D
52
1
51
Dimension in inch Symbol
E
Dimension in mm
Min
0.004 0.101 0.012 0.004 0.546 0.782 0.033 0.738 0.974 0.039
Nom
Max
0.130
Min
0.10
Nom
Max
3.30
E
H
19
33
20
e
b
32
c
2
A See Detail F Seating Plane
1
A
A A1 A2 b c D E e HD HE L L1 y
L L
1
0.107 0.016 0.006 0.551 0.787 0.039 0.748 0.984 0.047 0.098
0.113 0.020 0.010 0.556 0.792 0.045 0.758 0.994 0.055
2.57 0.30 0.10 13.87 19.87 0.85 18.75 24.75 1.00
2.72 0.40 0.15 14.00 20.00 1.00 19.00 25.00 1.20 2.50
2.87 0.50 0.25 14.13 20.13 1.15 19.25 25.25 1.40
0.004 0 12 0
0.10 12
y
A
Detail F
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
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